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SONY(R)
Description
CXK77B1841GB
45/5/6
4Mb Late Write LVTTL High Speed Synchronous SRAM (256K x 18 Organization)
The CXK77B1841 is a high speed BiCMOS synchronous static RAM with common I/O pins, organized as 262,144-words by 18-bits. This synchronous SRAM integrates input registers, high speed RAM, output registers/latches, and a one-deep write buffer onto a single monolithic IC. Three different read protocols - Register-Register (R-R), Register-Latch (R-L), and Registe rFlow Thru (R-FT), and an enhanced write protocol - Late (Delayed) Write (LW), are supported, providing a flexible, high-performance user interface. All input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the positive edge of K clock. Read cycles can be controlled in one of three ways - with registered outputs in Register-Register mode, with latched outputs in Register-Latch mode, or with flow-through outputs in Register-Flow Thru mode. The read protocol is user-selectable through external mode pins M1 and M2. Write cycles follow a Late Write protocol, where data is provided to the SRAM one clock cycle after the address and control signals, eliminating one dead cycle from Read-to-Write transitions. In this scheme, when a write cycle is initiated, the address and data stored in the SRAM's write buffer during the previous write cycle are directed to the SRAM's memory core, while, simultaneously, the address and data from the current write cycle are stored in the SRAM's write buffer. In both Register-Latch and Register-Flow Thru modes, when SW (Global Write Enable) is driven active, the subsequent positive edge of K clock tristates the SRAM's output drivers immediately, allowing consecutive Read-Write-Read operations. The write cycle is internally self-timed, which eliminates complex off-chip write pulse generation and provides increased flexibility for incoming signals. Sleep (power down) mode control is provided through the asynchronous ZZ input. 220 MHz operation is obtained from a single 3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
Features
* Fast Cycle/Access Time CXK77B1841 -45 -5 (*) -6 R-R Mode tKHKH / tKHQV 4.5ns / 2.4ns 5.0ns / 2.5ns 6.0ns / 3.0ns R-L, R-FT Modes tKHKH / tKHQV 5.5ns / 5.5ns 5.7ns / 5.7ns 6.0ns / 6.0ns
Note (*): Contact Sony Memory Marketing for availability of "-5" speed bin. * 3 synchronous modes of operation, selectable by mode pins: Register-Register; Register-Latch; Register-Flow Thru; * Single +3.3V power supply: 3.3V 5% * Dedicated output supply voltage: VDDQ (2.5V to 3.3V typical) * Inputs and outputs are LVTTL/LVCMOS compatible. * Differential clock input (K/K). Clock levels are compatible to PECL, LVTTL and LVCMOS. * All inputs (except asynchronous G and ZZ) and outputs are registered on a single clock edge. * Byte Write capability. * Late Write scheme to eliminate one dead cycle from Read-to-Write transitions. * Self-timed write cycles. * Sleep (power down) mode. * JTAG boundary scan (subset of IEEE standard 1149.1). * 119 pin (7x17) Plastic Ball Grid Array (PBGA) package.
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SONY(R)
CXK77B1841GB Pin Configuration (Top View) 1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQ0b NC VDDQ NC DQ3b VDDQ NC DQ5b VDDQ DQ7b NC NC NC VDDQ
2
SA6 NC SA12 NC DQ1b NC DQ2b NC VDD DQ4b NC DQ6b NC DQ8b SA10 SA17 TMS
3
SA7 SA8 SA5 VSS VSS VSS SBWb VSS NC VSS VSS VSS VSS VSS M1 SA9 TDI
4
NC NC VDD NC SS G C C VDD K K SW SA14 SA11 VDD NC TCK
5
SA3 SA4 SA0 VSS VSS VSS VSS VSS NC VSS SBWa VSS VSS VSS M2 SA1 TDO
6
SA2 NC SA13 DQ8a NC DQ6a NC DQ4a VDD NC DQ2a NC DQ1a NC SA15 SA16 NC
7
VDDQ NC NC NC DQ7a VDDQ DQ5a NC VDDQ DQ3a NC VDDQ NC DQ0a NC ZZ VDDQ
Pin Description
Symbol SA DQ K,K C,C SW SBWx SS Description Address Input (0-17) Data I/O (0-8), Bytes a,b Differential Input Clocks Differential Output Control Clocks (for future use) Write Enable, Global Write Enable, Bytes a,b Synchronous Select Symbol G ZZ TCK TMS TDI TDO VDD Description Async. Output Enable Async. Sleep Mode JTAG Clock (LVTTL) JTAG Mode Select (LVTTL) JTAG Data In (LVTTL) JTAG Data Out (LVTTL) +3.3V Power Supply Symbol V DDQ VSS M1,M2 NC Description Output Power Supply Ground Mode Select No Connect
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SONY(R)
CXK77B1841GB
BLOCK DIAGRAM
18 Input Reg. SA 0-17 Kint 2:1 Mux Write Store Reg.
Add. Dout 256K x 18 Write pulse Reg. Read Comp. Din 2:1 Mux
Output
^
latch
DQ
SS
Reg. Kint
^
SW
Reg. Kint 4
^ ^
Self Time Write Logic
SBW a-d
Reg. Kint
Input Clock 2 K/K Output Clock Mode Control
Kint
M1 M2
G
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CXK77B1841GB
*Truth Tables
Register - Register Mode
ZZ H L L L L L L SS (tn) X H L L L L L SW (tn) X X H H L L L SBWx (tn) X X X X L X H G X X H L X X X Mode Sleep Mode. Power Down Deselect Read Read Write All Bytes (Bits 0-17) Write Bytes With SBWx=L Abort Write DQ0-17 (tn) Hi - Z X Hi - Z X X X X DQ0-17 (tn+1) Hi - Z Hi - Z Hi - Z Q(tn) D(tn) D(tn) Hi - Z VDD Current ISB IDD IDD IDD IDD IDD IDD
Register - Latch and Register - Flow Thru Mode
ZZ H L L L L L L SS (tn) X H L L L L L SW (tn) X X H H L L L SBWx (tn) X X X X L X H G X X H L X X X Mode Sleep Mode. Power Down Deselect Read Read Write All Bytes (Bits 0-17) Write Bytes With SBWx=L Abort Write DQ0-17 (tn) Hi - Z Hi - Z Hi - Z Q(tn) Hi - Z Hi - Z Hi - Z DQ0-17 (tn+1) Hi - Z X Hi - Z X D(tn) D(tn) X VDD Current ISB IDD IDD IDD IDD IDD IDD
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CXK77B1841GB
*Mode Select
This device supports three different JEDEC standard read protocols via mode pins M1 and M2. The mode pins must be set during power-up and cannot change during SRAM operation. Mode Select Truth Table.
M1 Register-Register Register-Flow Thru Register-Latch L L H M2 H L L
*Power-Up Sequence
Power supplies must power up in the following sequence: VSS, VDD, VDDQ, and Inputs. VDDQ must never exceed VDD.
*Absolute Maximum Ratings(1)
Item Supply Voltage Output Supply Voltage Input Voltage Output Voltage Operating Temperature Junction Temperature Storage Temperature Symbol VDD VDDQ VIN VOUT TA TJ Tstg Rating -0.5 to +4.6 -0.5 to +4.6 -0.5 to VDD+0.5 (4.6V max.) -0.5 to VDDQ+0.5 (4.6V max.) 0 to 70 0 to 110 -55 to 150 Unit V V V V
C C C
(1) Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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CXK77B1841GB (VSS = 0V, TA = 0 to 70oC) Symbol
VDD VDDQ V IHCA VILCA VIHD VILD VKIN VDIF VCM VX VIH-PECL VIL-PECL
* DC Recommended Operating Conditions
Item
Supply Voltage Output Supply Voltage(1) Input High Voltage(2) Address & Control Input Low Voltage(4) Input High Voltage(3) Data Input Low Voltage(4) Input Signal Voltage Input Differential Voltage LVTTL Clock(5) Input Common Mode Voltage Input Cross Point Voltage
Min
3.13 2.37 1.65 -0.3 1.65 -0.3 -0.3 0.5 1.15 1.15 2.135 1.480
Typ
3.3 2.5, 3.3 ------------1.4 1.4 -----
Max
3.47 3.47 VDD + 0.3 1.15 VDDQ + 0.3 1.15 VDD + 0.3 VDD + 0.6 1.75 1.75 2.420 1.825
Unit
V V V V V V V V V V V V
PECL
(1) (2)
Input High Voltage Input Low Voltage
For VDDQ = 2.5V or VDDQ = 3.3V application. VIH (Max) AC = V DD+1.5 V for pulse width less than 2.0 ns (3) VIH (Max) AC = V DDQ+1.5 V for pulse width less than 2.0 ns (4) VIL (Min) AC = -1.5 V for pulse width less than 2.0 ns. (5) This device supports three different input clocking schemes: a. LVTTL Differential In this scheme, both clock inputs (K and K) are driven differentially to the same voltage levels as the other inputs, i.e. from VSS to VDDQ nominally. V KIN, VDIF, and VCM must all be considered when using this scheme.
b. LVTTL Single Ended - In this scheme, one of the two clock inputs (either K or K) is driven to the same voltage levels as the other inputs, i.e. from VSS to VDDQ nominally, while the other clock input (either K or K) is tied to an external reference voltage (VX). VKIN, VDIF, and VX must all be considered when using this scheme. c. PECL Differential In this scheme, both clock inputs (K and K) are driven differentially according to PECL guidelines. Both VIH-PECL and VIL-PECL must be considered when using this scheme. (TA = 25oC, f = 1 MHz)
*I/O Capacitance
Item Input Capacitance Clock Input Capacitance Output Capacitance Symbol CIN CCLK COUT Test conditions VIN = 0V VIN = 0V VOUT = 0V Min -------
Max 6 6 7
Unit pF pF pF
Note: These parameters are sampled and are not 100% tested.
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CXK77B1841GB
(VDD = 3.3V 5%, VSS = 0V, TA = 0 to 70oC)
*DC Electrical Characteristics
Item Input Leakage Current Output Leakage Current Power Supply Operating Current Power Supply Operating Current Power Supply Operating Current Power Supply Standby Current Output High Voltage VDDQ = 3.3V Output Low Voltage VDDQ = 3.3V Output High Voltage for VDDQ = 2.5V Output Low Voltage for VDDQ = 2.5V Symbol ILI ILO IDD1 Test Conditions VIN = VSS to VDD VOUT = VSS to VDD G = VIH Cycle = 6.0ns Duty = 100% IOUT = 0 mA Cycle = 5.5ns Duty = 100% IOUT = 0 mA Cycle = 4.5ns Duty = 100% IOUT = 0 mA VIH IOH = -6.0 mA IOL = 6.0 mA IOH = -6.0 mA IOL = 6.0 mA
Min -1 -10 ---
Typ ----600
Max 1 10 ---
Unit uA uA mA
IDD1
---
630
---
mA
IDD1
---
685
---
mA
ISB VOH VOL VOH VOL
--2.4 --2.0 ---
60 ---------
----0.4 --0.4
mA V V V V
1. Typical IDD values measured at VDD = 3.3V and TA = 25oC, with a 75% read / 25% write operation distribution.
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CXK77B1841GB
*AC Electrical Characteristics (Register-Register Mode)
-45 Item Symbol Min Cycle Time Clock High Pulse Width Clock Low Pulse Width Address Setup Time Address Hold Time Write Enables Setup Time Write Enables Hold Time Synchronous Select Setup Time Synchronous Select Hold Time Data Input Setup Time Data Input Hold Time Clock High to Output Valid Clock High to Output Hold Clock High to Output Low-Z Clock High to Output High-Z (SS Deselect Cycle) Output Enable Low to Output Valid Output Enable Low to Output Low-Z Output Enable High to Output High-Z Sleep Mode Enable Time Sleep Mode Recovery Time tKHKH tKHKL tKLKH tAVKH tKHAX tWVKH tKHWX tSVKH tKHSX tDVKH tKHDX tKHQV tKHQX*2 tKHQX1*2 tKHQZ*2 tGLQV tGLQX*2 tGHQZ*2 tZZE*2 tZZR*2 4.5 1.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 --0.7 0.7 ----0.5 ----20.0 Max ----------------------2.4 ----2.0 2.3 --2.3 20.0 --Min 5.0 1.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 --0.7 0.7 ----0.5 ----20.0 Max ----------------------2.5 ----2.0 2.5 --2.5 20.0 --Min 6.0 2.0 2.0 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 --0.7 0.7 ----0.5 ----20.0 Max ----------------------3.0 ----2.0 3.0 --3.0 20.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -5 -6 Unit
1. All parameters are specified over the range TA = 0 to 70oC. 2. These parameters are sampled and are not 100% tested.
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CXK77B1841GB
*AC Electrical Characteristics (Register-Latch & Register-Flow Thru Modes)
-45 Item Symbol Min Cycle Time Clock High Pulse Width Clock Low Pulse Width Address Setup Time Address Hold Time Write Enables Setup Time Write Enables Hold Time Synchronous Select Setup Time Synchronous Select Hold Time Data Input Setup Time Data Input Hold Time Clock High to Output Valid Clock High to Output Hold (Flow Thru mode only) Clock High to Output Low-Z (Flow Thru mode only) Clock Low to Output Valid (Latch mode only) Clock Low to Output Hold (Latch mode only) Clock Low to Output Low-Z (Latch mode only) Clock High to Output High-Z (SS Deselect Cycle) Clock High to Output High-Z (SW Write Cycle) Output Enable Low to Output Valid Output Enable Low to Output Low-Z Output Enable High to Output High-Z Sleep Mode Enable Time Sleep Mode Recovery Time tKHKH tKHKL tKLKH tAVKH tKHAX tWVKH tKHWX tSVKH tKHSX tDVKH tKHDX tKHQV tKHQX*2 tKHQX1*2 tKLQV tKLQX*2 tKLQX1*2 tKHQZ*2 tKHQZ1*2 tGLQV tGLQX*2 tGHQZ*2 tZZE*2 tZZR*2 5.5 1.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 --2.0 2.0 --0.7 0.7 ------0.5 ----20.0 Max ----------------------5.5 ----2.3 ----2.0 2.0 2.3 --2.3 20.0 --Min 5.7 1.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 --2.0 2.0 --0.7 0.7 ------0.5 ----20.0 Max ----------------------5.7 ----2.5 ----2.0 2.0 2.5 --2.5 20.0 --Min 6.0 2.0 2.0 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 --2.0 3.0 --0.7 0.7 ------0.5 ----20.0 Max ----------------------6.0 ----2.5 ----2.0 2.0 2.5 --2.5 20.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -5 -6 Unit
1. All parameters are specified over the range TA = 0 to 70oC. 2. These parameters are sampled and are not 100% tested.
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CXK77B1841GB
*AC Test Conditions (VDDQ = 2.5V)
(VDD = 3.3V 5%, VDDQ = 2.5V -5%/+10%, TA = 0 to 70C)
Item Address / Control / Data Input High Level Address / Control / Data Input Low Level Input Rise & Fall Time Input Reference Level Clock LVTTL Input High Voltage LVTTL Input Low Voltage LVTTL Input Common Mode Voltage PECL Input High Voltage PECL Input Low Voltage Clock Input Rise & Fall Time Clock Input Reference Level Output Reference Level Output Load Conditions
Conditions VIHCA, VIHD = 2.0V VILCA, VILD = 0.8V 1.0V/ns 1.4V 2.2V 0.6V 1.4V VIH-PECL = 2.3V VIL-PECL = 1.6V 1.0V/ns K/K cross 1.25V Fig.1
Notes @ Set up time 1ns @ Set up time 1ns Other than Clock Other than Clock
VDIF 0.8V VDIF 0.8V
Fig. 1: AC Test Output Load (VDDQ = 2.5V)
16.7 50
1.25 V 50 5 pF
DQ
16.7
1.25 V 16.7 50 5 pF 50
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CXK77B1841GB
*AC Test Conditions (VDDQ = 3.3V)
(VDD = VDDQ = 3.3V 5%, TA = 0 to 70C)
Item Address / Control / Data Input High Level Address / Control / Data Input Low Level Input Rise & Fall Time Input Reference Level Clock LVTTL Input High Voltage LVTTL Input Low Voltage LVTTL Input Common Mode Voltage PECL Input High Voltage PECL Input Low Voltage Clock Input Rise & Fall Time Clock Input Reference Level Output Reference Level Output Load Conditions
Conditions VIHCA, VIHD = 2.4V VILCA, VILD = 0.4V 1.0V/ns 1.4V 2.4V 0.4V 1.4V VIH-PECL = 2.3V VIL-PECL = 1.6V 1.0V/ns K/K cross 1.4V Fig.2
Notes @ Set up time 1ns @ Set up time 1ns Other than Clock Other than Clock
VDIF 1.0V VDIF 1.0V
Fig. 2: AC Test Output Load (VDDQ = 3.3V)
16.7 50
1.4 V 50 5 pF
DQ
16.7
1.4 V 16.7 50 5 pF 50
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CXK77B1841GB
Register - Register Mode
TIMING WAVEFORM OF READ CYCLE
K K
tKHKH tKHKL tKLKH
SA0-SA17
n
tAVKH tKHAX
n+1
n+2
SW
tWVKH tKHWX tSVKH tKHSX
SS
tKHQV tKHQV tGLQV
G
tKHQX1 tGHQZ tGLQX tKHQZ
DQ0-DQ17
Qn-2
Qn-1
Qn
TIMING WAVEFORM OF WRITE CYCLE
K K SA0-SA17 SS SW/SBWx G
tDVKH tKHDX
n
n+1
n+2
DQ0-DQ17
Dn-1
Dn
Dn+1
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CXK77B1841GB
Register - Register Mode
TIMING WAVEFORM OF READ-WRITE-READ CYCLE I (SS controlled)
K K SA0-SA17 SS SW/SBWx G = VIL DQ0-DQ17 Qn-1 Read N Qn Deselect (Hi Z) Dn+2 Write N+2 Read N+3 Qn+3 n n+2 n+3 n+4 n+5
TIMING WAVEFORM OF READ-WRITE-READ CYCLE II (G controlled)
K K SA0-SA17 SS = VIL SW/SBWx G DQ0-DQ17 Qn-1 Read N Qn Dn+2 Hi Z; Write N+2 Read N+3 Qn+3 n n+2 n+3 n+4 n+5
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CXK77B1841GB
Register - Latch Mode
TIMING WAVEFORM OF READ CYCLE
K
K
tKHKH tKHKL tKLKH
SA0-SA17
n
tAVKH tKHAX
n+1
n+2
SW
tWVKH tKHWX
tSVKH tKHSX
tSVKH tKHSX
SS
tKLQV tKHQV tKHQV tGLQV tKLQX1 tGHQZ tGLQX tKHQZ tKLQV
G
DQ0-DQ17
Qn-1
Qn
Qn+1
TIMING WAVEFORM OF WRITE CYCLE
K K SA0-SA17 SS SW/SBWx G
tDVHK tKHDX tKHKH
n
n+1
n+2
DQ0-DQ17
Dn-1
Dn
Dn+1
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CXK77B1841GB
Register - Latch Mode
TIMING WAVEFORM OF READ-WRITE-READ CYCLE
K K SA0-SA17 SS SW/SBWx G = VIL DQ0-DQ17
tKHKH tKHKH tKHKH tKHKH
n
tAVKH tKHAX
n+1
tWVKH tKHWX
n+2
n+3
tSVKHtKHSX
n+4
n+5
tKLQV tKLQV tKHQV tKHQZ1 tKHQV tDVKH tKHDX tKHQZ tKLQX1 tKLQV
Qn Read N Write N+1
Dn+1 Read N+2
Qn+2 Deselect (Hi Z) Read N+4
Qn+4
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CXK77B1841GB
Register - Flow Thru Mode
TIMING WAVEFORM OF READ CYCLE
K
K
tKHKH tKHKL tKLKH
SA0-SA17
n
tAVKH tKHAX
n+1
n+2
SW
tWVKH tKHXW tSVKH tKHSX tSVKH tKHSX
SS
tKHQV tKHQV tGLQV
G
tKHQX1 tGHQZ tGLQX tKHQZ
DQ0-DQ17
Qn-1
Qn
Qn+1
TIMING WAVEFORM OF WRITE CYCLE
K K SA0-SA17 SS SW/SBWx G
tDVKH tKHDX
n
n+1
n+2
DQ0-DQ17
Dn-1
Dn
Dn+1
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CXK77B1841GB
Register - Flow Thru Mode
TIMING WAVEFORM OF READ-WRITE-READ CYCLE
K K SA0-SA17 SS SW/SBWx
tKHQV tKHQZ1
n
tAVKH tKHAX
n+1
tWVKH tKHWX
n+2
n+3
tSVKH tKHSX
n+4
n+5
tKHQV tDVKH tKHDX tKHQZ tKHQV
G = VIL DQ0-DQ17 Qn Read N Write N+1 Dn+1 Read N+2 Qn+2
tKHQX1
Qn+4 Read N+4
Deselect (Hi Z)
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Test Mode Description
Functional Description
CXK77B1841GB
The CXK77B1841 provides a JTAG boundary scan interface using a limited set of IEEE std. 1149.1 functions. The test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), SRAMs, other components and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, the CXK77B1841 contains a TAP controller, Instruction register, Boundary scan register and Bypass register. JTAG Inputs/Outputs are LVTTL compatible only. Test Access Port (TAP) 4 pins as defined in the Pin Description table are used to perform JTAG functions. The TDI input pin is used to scan test data serially into one of three registers (Instruction register, Boundary Scan register and Bypass register). TDO is the output pin used to scan test data serially out. The TDI pin sends the data into LSB of the selected register and the MSB of the selected register feeds the data to TDO. The TMS input pin controls the state transition of 16 state TAP controller as specified in IEEE std. 1149.1. Inputs on TDI and TMS are registered on the rising edge of TCK clock. The output data on TDO is presented on the falling edge of TCK. TDO driver is in active state only when TAP controller is in Shift-IR state or in Shift-DR state. TCK, TMS, TDI must be tied low when JTAG is not used. TAP Controller 16 state controller is implemented as specified in IEEE std. 1149.1. The controller enters reset state in one of two ways: 1. Power up. 2. Apply a logic 1 on TMS input pin on 5 consecutive TCK rising edges. Instruction Register (3 bits) The JTAG Instruction register consists of a shift register stage and parallel output latch. The register is 3 bits wide and is encoded as follow: Octal 0 1 2 3 4 5 6 7
256Kx18, Sync LW, LVTTL, rev 4.6
MSB..........LSB 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Instruction Bypass IDCODE. Read device ID Sample-Z. Sample Inputs and tri-state DQs Bypass Sample. Sample Inputs. Private. Manufacturer use only. Bypass Bypass
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Bypass Register (1 bit)
CXK77B1841GB
The Bypass Register is one bit wide and is connected electrically between TDI and TDO and provides the minimum length serial path between TDI and TDO. ID Registers (32 bits) The ID Register is 32 bits wide and is encoded as follows:
ID[0} Sony ID Part Number Revision Number ID[11:1] ID[27:12] ID[31:28]
1 0000 1110 001 0000 0000 0001 1010 xxxx
Boundary Scan Register (51 bits) The Boundary Scan Registers are 51 bits wide and are listed as follows:
DQ SA SW, SBWx SS, G K, K, C, C ZZ M1, M2 Place Holder TNC
18 18 3 2 4 1 2 2 1
K/K, C/C inputs are sampled through one differential stage and internally inverted to generate internal K/K, C/C signals for scan registers. Place Holder are required for some NC pins to maintain 51 bits Scan Register for different types of the same family SRAM and for density upgrades. All Place Holder Registers are connected to VSS internally regardless of pin connection externally. TNC register is True No Connect i.e. not connected internally. TNC register information should be ignored during BSCAN testing.
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Scan Order (Order by exit sequence)
CXK77B1841GB
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
3B 3A 3C 2C 2A 1D 2E 2G 1H 3G 4D 4E 4G 4H 4M 2K 1L 2M 1N 2P 3T 2R 4N 2T 3R
SA VSS SA SA SA SA DQb DQb DQb DQb SBWb
TNC(*)
SS C C SW DQb DQb DQb DQb DQb SA SA SA SA M1
SA VSS SA SA SA SA DQa DQa DQa DQa DQa G K K SBWa DQa DQa DQa DQa ZZ SA SA SA SA M2
5B 5A 5C 6C 6A 6D 7E 6F 7G 6H 4F 4K 4L 5L 7K 6L 6N 7P 7T 5T 6R 4P 6T 5R
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
(*) TNC means that the voltage polarity of this bit should be ignored during boundary scan testing.
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Ordering Information.
Part Number
CXK77B1841GB
Speed
Register - Register Register - Latch/ Register - Flow Thru 5.5ns Cycle / 5.5ns Access 5.7ns Cycle / 5.7ns Access 6.0ns Cycle / 6.0ns Access
CXK77B1841GB-45 CXK77B1841GB-5 (*) CXK77B1841GB-6
4.5ns Cycle / 2.4ns Access 5.0ns Cycle / 2.5ns Access 6.0ns Cycle / 3.0ns Access
Note (*): Contact Sony Memory Marketing for availability of "-5" speed bin.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
256Kx18, Sync LW, LVTTL, rev 4.6
21 / 22
August 12, 1998
SONY(R)
Revision History Rev. # rev 4.0 rev 4.2 (Unreleased) Rev. date 8/22/97 11/21/97
CXK77B1841GB
Changes / Modifications to Data-Sheet Initial version, based on TS-2 evaluation Modified AC Electrical Characteristics: R-L, R-FT Modes: -6 TKLQV, TGLQV, TGHQZ TKHQZ, TKHQZ1 TKHQX1 Renamed "-4.5" bin to "-45" bin in all modes. Renamed "-5" bin to "-50" bin in all modes. Renamed "-6" bin to "-60" bin in all modes. Added "-65" bin to all modes. Provided IDD & ISB typical values (page-7) Provided PECL DC electrical characteristic (page-6) Provided PECL AC test conditions (page-10, -11)
3.0ns to 2.5ns 3.0ns to 2.0ns 2.0ns to 3.0ns
rev 4.3 rev 4.4 rev 4.5
01/05/98 01/15/98 03/12/98
Updated DC Recommended Operating Conditions (page-6) Updated AC Test Conditions for VDDQ = 2.5V (page-10) Deleted "-65" bins. Renamed "-50" bin to "-5" bin in all modes. Renamed "-60" bin to "-6" bin in all modes. Changed BSCAN register # 37 from VSS to TNC (page-20) Modified BSCAN register table to include TNC (page-19) TKHQZ & TKHQZ1 AC timing changed to 2.0ns for all bins (page-8 &-9) Changed VDIF (min) DC parameter from 0.4V to 0.5V (page-6) Changed VCM (min) DC parameter from 1.2V to 1.15V (page-6) Changed VCM (typ) DC parameter from VDDQ/2 to 1.4V (page-6) Deleted LVTTL Clock VIH and VIL DC parameters (page-6) Added LVTTL Clock VKIN DC parameter (page-6) Added LVTTL Clock VX DC parameter (page-6) Added Note 5 (Clock description) to DC Recommendations (page-6) Rearranged AC Test Conditions (page-10 & page-11) Removed "Preliminary" from the spec.
rev 4.6
08/12/98
Modified AC Electrical Characteristics: R-R Mode: -45 TKHQV
2.3ns to 2.4ns
256Kx18, Sync LW, LVTTL, rev 4.6
22 / 22
August 12, 1998

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